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| author |   Sean Christopherson <seanjc@google.com> | 2021-05-04 10:17:30 -0700 |
|---|---|---|
| committer |   Paolo Bonzini <pbonzini@redhat.com> | 2021-05-07 06:06:18 -0400 |
| commit | 5e17c624010a82bbcca9b955155781927eb6532a (patch) | |
| tree | 79f93fe027e29bf8706a0a8193c216f6ef1de15a /tools/perf/scripts/python/syscall-counts.py | |
| parent | KVM: VMX: Use common x86's uret MSR list as the one true list (diff) | |
| download | wireguard-linux-5e17c624010a82bbcca9b955155781927eb6532a.tar.xz wireguard-linux-5e17c624010a82bbcca9b955155781927eb6532a.zip | |
KVM: VMX: Disable loading of TSX_CTRL MSR the more conventional way
Tag TSX_CTRL as not needing to be loaded when RTM isn't supported in the
host. Crushing the write mask to '0' has the same effect, but requires
more mental gymnastics to understand.
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20210504171734.1434054-12-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions