diff options
| author |   Stratos Karafotis <stratosk@semaphore.gr> | 2014-03-19 23:29:17 +0200 |
|---|---|---|
| committer |   Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2014-03-20 03:39:28 +0100 |
| commit | e5c87b762871c3377e456f6a57769dc63bdddd4b (patch) | |
| tree | 04b2582ac53f1010bd7c24896e70500335212446 /tools/perf/scripts/python/syscall-counts.py | |
| parent | cpufreq: powerpc: add cpufreq transition latency for FSL e500mc SoCs (diff) | |
| download | wireguard-linux-e5c87b762871c3377e456f6a57769dc63bdddd4b.tar.xz wireguard-linux-e5c87b762871c3377e456f6a57769dc63bdddd4b.zip | |
cpufreq: Fix checkpatch errors and warnings
Fix 2 checkpatch errors about using assignment in if condition,
1 checkpatch error about a required space after comma
and 3 warnings about line over 80 characters.
Signed-off-by: Stratos Karafotis <stratosk@semaphore.gr>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions