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| author |   Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> | 2023-06-05 13:23:58 +0200 |
|---|---|---|
| committer |   Michal Simek <michal.simek@amd.com> | 2023-07-10 12:04:49 +0200 |
| commit | 3011e0c8139323af4e449bb4c7dce63aedc33808 (patch) | |
| tree | 3d0313f669f03748101fa0e1bac24c21f5ecdebd /tools/perf/scripts/python/task-analyzer.py | |
| parent | Linux 6.5-rc1 (diff) | |
| download | wireguard-linux-3011e0c8139323af4e449bb4c7dce63aedc33808.tar.xz wireguard-linux-3011e0c8139323af4e449bb4c7dce63aedc33808.zip | |
arm64: zynqmp: Add L2 cache nodes
Describe SoC L2 cache hierarchy.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/130e5a6acbee94809b63a61cde5450fbff88cc9c.1685964230.git.michal.simek@amd.com
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
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