diff options
| author |   Ravi Bangoria <ravi.bangoria@amd.com> | 2022-09-28 15:27:54 +0530 |
|---|---|---|
| committer |   Peter Zijlstra <peterz@infradead.org> | 2022-09-29 12:20:55 +0200 |
| commit | 6b2ae4952ef8ac23b467bc10776404092b581143 (patch) | |
| tree | 210d6dfacc49a8f743e10205ec2b567de2d52ea5 /tools/perf/scripts/python/task-analyzer.py | |
| parent | perf/x86/amd: Support PERF_SAMPLE_DATA_SRC (diff) | |
| download | wireguard-linux-6b2ae4952ef8ac23b467bc10776404092b581143.tar.xz wireguard-linux-6b2ae4952ef8ac23b467bc10776404092b581143.zip | |
perf/x86/amd: Support PERF_SAMPLE_{WEIGHT|WEIGHT_STRUCT}
IbsDcMissLat indicates the number of clock cycles from when a miss is
detected in the data cache to when the data was delivered to the core.
Similarly, IbsTagToRetCtr provides number of cycles from when the op
was tagged to when the op was retired. Consider these fields for
sample->weight.
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20220928095805.596-5-ravi.bangoria@amd.com
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions