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| author |   Ira Weiny <ira.weiny@intel.com> | 2023-01-17 21:53:40 -0800 |
|---|---|---|
| committer |   Dan Williams <dan.j.williams@intel.com> | 2023-01-26 16:51:07 -0800 |
| commit | 95b4947992858f725ad6a65a2087a3533749660f (patch) | |
| tree | a152013ff4ea36d8accf7d7ca55e460840312d26 /tools/perf/scripts/python/task-analyzer.py | |
| parent | cxl/mem: Trace DRAM Event Record (diff) | |
| download | wireguard-linux-95b4947992858f725ad6a65a2087a3533749660f.tar.xz wireguard-linux-95b4947992858f725ad6a65a2087a3533749660f.zip | |
cxl/mem: Trace Memory Module Event Record
CXL rev 3.0 section 8.2.9.2.1.3 defines the Memory Module Event Record.
Determine if the event read is memory module record and if so trace the
record.
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Link: https://lore.kernel.org/r/20221216-cxl-ev-log-v7-5-2316a5c8f7d8@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
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