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| author |   Raviteja Narayanam <raviteja.narayanam@xilinx.com> | 2023-02-15 19:02:23 +0530 |
|---|---|---|
| committer |   Wolfram Sang <wsa@kernel.org> | 2023-02-17 22:43:06 +0100 |
| commit | 9b97cd61ee1ca7ba9a7005afd52f963a811b492c (patch) | |
| tree | 531aaea7f328bc3bd7c0478faaca86919a794639 /tools/perf/scripts/python/task-analyzer.py | |
| parent | dt-bindings: i2c: xiic: Add 'xlnx,axi-iic-2.1' to compatible (diff) | |
| download | wireguard-linux-9b97cd61ee1ca7ba9a7005afd52f963a811b492c.tar.xz wireguard-linux-9b97cd61ee1ca7ba9a7005afd52f963a811b492c.zip | |
i2c: xiic: Update compatible with new IP version
Xilinx AXI I2C IP is updated with a bug fix for dynamic mode reads.
Older IPs are handled with a workaround in which they are using
xiic standard mode for all these effected use cases.
Add the new IP version to compatible.
Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions