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| author |   Vinay Belgaumkar <vinay.belgaumkar@intel.com> | 2021-07-30 13:21:16 -0700 |
|---|---|---|
| committer |   John Harrison <John.C.Harrison@Intel.com> | 2021-08-03 16:05:38 -0700 |
| commit | 025cb07bebfaf9e3703f902cce92b4656129a62b (patch) | |
| tree | 79f421a597b17acaa622f695088c5dacb3f2ae9a /tools/perf/scripts/python | |
| parent | drm/i915/guc/slpc: Enable ARAT timer interrupt (diff) | |
| download | wireguard-linux-025cb07bebfaf9e3703f902cce92b4656129a62b.tar.xz wireguard-linux-025cb07bebfaf9e3703f902cce92b4656129a62b.zip | |
drm/i915/guc/slpc: Cache platform frequency limits
Cache rp0, rp1 and rpn platform limits into SLPC structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland. These are initially set to platform min
and max.
v2: Address review comments (Michal W)
v3: Formatting (Michal W)
v4: Add separate function to parse rp values (Michal W)
v5: Perform range checking for set min/max (Michal W)
v6: checkpatch() and rename static functions (Michal W)
v7: check ret code while setting SLPC limits (Michal W)
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210730202119.23810-12-vinay.belgaumkar@intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions