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| author |   Jean-Jacques Hiblot <jjhiblot@traphandler.com> | 2022-02-21 10:50:29 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-02-24 13:48:45 +0100 |
| commit | 045d0625d305b2c99aba60f787250483af4a23a4 (patch) | |
| tree | 90d56a5d3ca4dd0a39d9c701d32d3c4993651681 /tools/perf/scripts/python | |
| parent | dt-bindings: clock: r9a06g032: Add the definition of the watchdog clock (diff) | |
| download | wireguard-linux-045d0625d305b2c99aba60f787250483af4a23a4.tar.xz wireguard-linux-045d0625d305b2c99aba60f787250483af4a23a4.zip | |
ARM: dts: r9a06g032: Add the watchdog nodes
This SoC includes 2 watchdog controllers (one per A7 core).
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
Link: https://lore.kernel.org/r/20220221095032.95054-4-jjhiblot@traphandler.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions