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| author |   Sebastian Reichel <sebastian.reichel@collabora.com> | 2025-08-18 19:12:23 +0200 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2025-08-24 12:17:45 +0200 |
| commit | 09cce878427962a5c2a3a37d6cc52485a0134ac1 (patch) | |
| tree | ecf82585a660a47c5283f5a276836ea639a0733e /tools/perf/scripts/python | |
| parent | arm64: dts: rockchip: Minor whitespace cleanup (diff) | |
| download | wireguard-linux-09cce878427962a5c2a3a37d6cc52485a0134ac1.tar.xz wireguard-linux-09cce878427962a5c2a3a37d6cc52485a0134ac1.zip | |
arm64: dts: rockchip: correct network description on Sige5
Both network PHYs have dedicated crystals for the 25 MHz clock
and do not source it from the RK3576.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250818-sige5-network-phy-clock-v1-1-87a9122d41c2@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions