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| author |   Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> | 2019-09-08 07:42:25 -0700 |
|---|---|---|
| committer |   Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2019-09-09 13:19:35 +0300 |
| commit | 1233c7b95c7045905e40c11484493f20ab521d21 (patch) | |
| tree | 31f18b1f9ff7a36e84418c7f43aa15c5145fd4df /tools/perf/scripts/python | |
| parent | platform/x86: ISST: Allow additional TRL MSRs (diff) | |
| download | wireguard-linux-1233c7b95c7045905e40c11484493f20ab521d21.tar.xz wireguard-linux-1233c7b95c7045905e40c11484493f20ab521d21.zip | |
tools/power/x86/intel-speed-select: Display core count for bucket
Read the bucket and core count relationship via MSR and display
when displaying turbo ratio limits.
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions