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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-05-13 23:41:22 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-05-23 21:11:11 +0300 |
| commit | 14d41b3b0e2ffbed309e68c87031986016d7bcac (patch) | |
| tree | b1036bc7aca1a5f0dfd2aa419a199733d4b1ce61 /tools/perf/scripts/python | |
| parent | drm/i915/skl: SKL CDCLK change on modeset tracking VCO (diff) | |
| download | wireguard-linux-14d41b3b0e2ffbed309e68c87031986016d7bcac.tar.xz wireguard-linux-14d41b3b0e2ffbed309e68c87031986016d7bcac.zip | |
drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config()
Shared plls won't get assigned until the .compute_clocks() hook gets
called, which happens from the crtc .atomic_check hook. That's too late
as the cdclk computation has already happened. So let's move the DPLL0
VCO computation into intel_dp_compute_config() so that it's done when
the cdclk computation happens. Also only do it for eDP since we only
pick DPLL0 for eDP.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-4-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions