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| author |   Hsin-Yi Wang <hsinyi@chromium.org> | 2021-03-30 19:04:23 +0800 |
|---|---|---|
| committer |   Matthias Brugger <matthias.bgg@gmail.com> | 2021-03-31 13:52:52 +0200 |
| commit | 1ff1270fca33c582b53b51dc2903f21ae7e1f4bc (patch) | |
| tree | e8fa8daab51687525e1cafbee391076852c8ec3d /tools/perf/scripts/python | |
| parent | soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs (diff) | |
| download | wireguard-linux-1ff1270fca33c582b53b51dc2903f21ae7e1f4bc.tar.xz wireguard-linux-1ff1270fca33c582b53b51dc2903f21ae7e1f4bc.zip | |
soc: mediatek: mmsys: Add mt8183 mmsys routing table
mt8183 has different routing registers than mt8173.
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20210330110423.3542163-1-hsinyi@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions