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| author |   Adrian Hunter <adrian.hunter@intel.com> | 2025-07-23 19:58:56 +0300 |
|---|---|---|
| committer |   Martin K. Petersen <martin.petersen@oracle.com> | 2025-07-24 22:37:30 -0400 |
| commit | 22b246e3fc5eb450fffad1eb322e08e3af0e6e3d (patch) | |
| tree | b7388eb16d46c2e7121ca4855c6be9d0590f5b7c /tools/perf/scripts/python | |
| parent | scsi: ufs: core: Do not write interrupt enable register unnecessarily (diff) | |
| download | wireguard-linux-22b246e3fc5eb450fffad1eb322e08e3af0e6e3d.tar.xz wireguard-linux-22b246e3fc5eb450fffad1eb322e08e3af0e6e3d.zip | |
scsi: ufs: ufs-pci: Remove control of UIC Completion interrupt for Intel MTL
Now that UFS core enables the UIC Completion interrupt only when needed,
Intel MTL driver no longer needs to control the interrupt itself. So
remove the associated code.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20250723165856.145750-9-adrian.hunter@intel.com
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions