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| author |   Maarten Zanders <maarten.zanders@mind.be> | 2022-10-28 17:26:23 +0200 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2022-11-25 19:31:52 +0000 |
| commit | 27b6fa6145215c5f49d93e322a16144b928ecd3e (patch) | |
| tree | 823efc3fb1c444b598b88b8b06a600181429b2e3 /tools/perf/scripts/python | |
| parent | Linux 6.1-rc5 (diff) | |
| download | wireguard-linux-27b6fa6145215c5f49d93e322a16144b928ecd3e.tar.xz wireguard-linux-27b6fa6145215c5f49d93e322a16144b928ecd3e.zip | |
ASoC: adau1372: fix mclk
"mclk" is retrieved from the configuration and assigned to adau1372->clk.
However adau1372->mclk (==NULL) is used for clk_prepare_enable() and
clk_disable_unprepare() which don't have any effect.
Remove .clk from struct adau1372 and use .mclk throughout.
This change ensures that the input clock is switched on/off when the
bias level is changed.
Signed-off-by: Maarten Zanders <maarten.zanders@mind.be>
Link: https://lore.kernel.org/r/20221028152626.109603-2-maarten.zanders@mind.be
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions