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author | 2016-03-07 17:17:37 +0200 | |
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committer | 2016-04-11 12:48:52 -0700 | |
commit | 296ea972dc96a78cc26027e879db91273c91f3c4 (patch) | |
tree | 99c74611b3ef000966f2d8e685e1f1961c6deffe /tools/perf/scripts/python | |
parent | ARM: dts: dra7xx: Correct mcasp8_ahclkx_mux name (diff) | |
download | wireguard-linux-296ea972dc96a78cc26027e879db91273c91f3c4.tar.xz wireguard-linux-296ea972dc96a78cc26027e879db91273c91f3c4.zip |
ARM: dts: dra7: Add nodes for McASP1/2/4/5/6/7/8
Add nodes to represent all McASP ports in the dra7 family.
For system consistency use the eDMA for audio operations. sDMA would be
fine for 4/5/6/7/8 since their DAT port is not through L3 interconnect.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions