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| author |   Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-07-17 10:30:40 +0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2023-07-20 17:22:30 +0100 |
| commit | 3e6670a28b009cc381b40ee26a6f41509aca46eb (patch) | |
| tree | 452792bdd82c09844dc1d0d726118239d012e6a3 /tools/perf/scripts/python | |
| parent | riscv: dts: starfive: jh7110: Add syscon nodes (diff) | |
| download | wireguard-linux-3e6670a28b009cc381b40ee26a6f41509aca46eb.tar.xz wireguard-linux-3e6670a28b009cc381b40ee26a6f41509aca46eb.zip | |
riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node
Add PLL clocks input from PLL clocks driver in SYSCRG node.
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions