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| author |   Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> | 2025-10-15 10:12:42 +0800 |
|---|---|---|
| committer |   Dinh Nguyen <dinguyen@kernel.org> | 2025-11-04 15:25:44 -0600 |
| commit | 3e99d51aaaba3ed3f092f635ad053fe1ca5953ff (patch) | |
| tree | 4cbb0279f419608187fa4ece839b254454beeb37 /tools/perf/scripts/python | |
| parent | arm64: dts: socfpga: agilex5: fix CHECK_DTBS warning for NAND (diff) | |
arm64: dts: socfpga: agilex5: Add L2 and L3 cache
Add L2 and L3 cache nodes to the device tree to resolve the
"unable to detect cache hierarchy" warning reported by cacheinfo.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions