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| author |   Mihai Sain <mihai.sain@microchip.com> | 2025-06-19 10:06:35 +0300 |
|---|---|---|
| committer |   Claudiu Beznea <claudiu.beznea@tuxon.dev> | 2025-07-05 10:43:30 +0300 |
| commit | 4101c8274b093519019761e174c81980f7b30f56 (patch) | |
| tree | b096c39c1b52dd315ff6f5c8aca1bc9d697ce0d2 /tools/perf/scripts/python | |
| parent | ARM: dts: microchip: sama5d4: Update the cache configuration for CPU (diff) | |
| download | wireguard-linux-4101c8274b093519019761e174c81980f7b30f56.tar.xz wireguard-linux-4101c8274b093519019761e174c81980f7b30f56.zip | |
ARM: dts: microchip: sama7d65: Add cache configuration for cpu node
Describe the cache memories according with datasheet chapter 15.2:
- L1 cache configuration with 32KB for both data and instruction cache.
- L2 cache configuration with 256KB unified cache.
Before this patch the kernel reported the warning:
[ 0.161955] cacheinfo: Unable to detect cache hierarchy for CPU 0
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250619070636.8844-2-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions