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| author |   Liu Ying <victor.liu@nxp.com> | 2025-07-07 10:47:00 +0800 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2025-07-22 18:48:31 +0530 |
| commit | 429efeb1900d4a3164e1233b392ee5f489b6c3f8 (patch) | |
| tree | 676a5b47e02dcc362a34ce3dfc924b4704c9b3c8 /tools/perf/scripts/python | |
| parent | phy: exynos-mipi-video: correct cam0 sysreg property name for exynos7870 (diff) | |
| download | wireguard-linux-429efeb1900d4a3164e1233b392ee5f489b6c3f8.tar.xz wireguard-linux-429efeb1900d4a3164e1233b392ee5f489b6c3f8.zip | |
dt-bindings: phy: mixel, mipi-dsi-phy: Allow assigned-clock* properties
assigned-clock* properties can be used by default now, so allow them.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250707-dt-bindings-phy-mixel-mipi-dsi-phy-allow-assign-clock-properties-v1-1-5e34b257e1ef@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions