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| author |   Stephen Boyd <sboyd@kernel.org> | 2025-07-21 17:34:01 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-07-21 17:34:01 -0700 |
| commit | 53afec24ec9dd8e8459ca1634fef2f8c958fbc65 (patch) | |
| tree | 7de65f84583b6ad9910e5036c3b2f29776e74319 /tools/perf/scripts/python | |
| parent | Linux 6.16-rc1 (diff) | |
| parent | clk: at91: sam9x7: update pll clk ranges (diff) | |
| download | wireguard-linux-53afec24ec9dd8e8459ca1634fef2f8c958fbc65.tar.xz wireguard-linux-53afec24ec9dd8e8459ca1634fef2f8c958fbc65.zip | |
Merge tag 'clk-microchip-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip
Microchip clock updates for v6.17
- Fix the PLL output ranges for Microchip SAM9X7, based on the
latest hardware documentation updates
* tag 'clk-microchip-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
clk: at91: sam9x7: update pll clk ranges
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions