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| author |   Kevin Lo <kevlo@kevlo.org> | 2019-08-01 11:29:38 +0800 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2019-08-02 18:17:06 -0700 |
| commit | 59c0b47a1e11b5e81ab1dfd13579c9fbdb02f0b4 (patch) | |
| tree | 7e6de377bbebc8e55c2194395d787eb836b24697 /tools/perf/scripts/python | |
| parent | net: phy: fix race in genphy_update_link (diff) | |
| download | wireguard-linux-59c0b47a1e11b5e81ab1dfd13579c9fbdb02f0b4.tar.xz wireguard-linux-59c0b47a1e11b5e81ab1dfd13579c9fbdb02f0b4.zip | |
r8152: fix typo in register name
It is likely that PAL_BDC_CR should be PLA_BDC_CR.
Signed-off-by: Kevin Lo <kevlo@kevlo.org>
Acked-by: Hayes Wang <hayeswang@realtek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions