diff options
| author |   Jouni Högander <jouni.hogander@intel.com> | 2025-07-22 15:56:18 +0300 |
|---|---|---|
| committer |   Tvrtko Ursulin <tursulin@ursulin.net> | 2025-07-29 10:20:33 +0100 |
| commit | 5a569ef4d4ab184a481dd8ecb58f464a89b44d2f (patch) | |
| tree | 343d0c05cf7b7447f9a37d40524a7f714e978ecb /tools/perf/scripts/python | |
| parent | drm/i915/display: Ensure phy is accessible on lfps configuration (diff) | |
| download | wireguard-linux-5a569ef4d4ab184a481dd8ecb58f464a89b44d2f.tar.xz wireguard-linux-5a569ef4d4ab184a481dd8ecb58f464a89b44d2f.zip | |
drm/i915/display: Set C10_VDR_CTRL_MSGBUS_ACCESS before phy reg read
According to C10 VDR Register programming sequence we need set
C10_VDR_CTRL_MSGBUS_ACCESS before accessing PHY internal registers from
MsgBus.
v2: set C10_VDR_CTRL_MSGBUS_ACCESS once for all owned lanes
Bspec: 68962
Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure LFPS sending")
Suggested-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20250722125618.1842615-5-jouni.hogander@intel.com
(cherry picked from commit 8921dce70d46e3156b5a0b21675f5ac90903d81d)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions