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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-06-27 21:42:32 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-07-02 20:19:48 +0200 |
| commit | 5e4e8c1415c181ce311a0b5936ef301edd57c5d1 (patch) | |
| tree | 95858be50b78b6c4550bb52c1f903b1d9850464d /tools/perf/scripts/python | |
| parent | Linux 6.16-rc1 (diff) | |
| download | wireguard-linux-5e4e8c1415c181ce311a0b5936ef301edd57c5d1.tar.xz wireguard-linux-5e4e8c1415c181ce311a0b5936ef301edd57c5d1.zip | |
dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
Add XSPI core clock definitions to the clock bindings for the Renesas
R9A09G056 and R9A09G057 SoCs. These clocks IDs are used to support XSPI
interface.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250627204237.214635-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions