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| author |   Michel Dänzer <michel.daenzer@amd.com> | 2015-07-17 11:20:18 +0900 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2015-07-23 11:09:43 -0400 |
| commit | 5e6775abb5ce7ada76fa17c67857576176d0b60f (patch) | |
| tree | a3c3ec3f863bed4e592982f2f594bbda6ca5bc5f /tools/perf/scripts/python | |
| parent | drm/amdgpu/dce11: Re-set VBLANK interrupt state when enabling a CRTC (diff) | |
| download | wireguard-linux-5e6775abb5ce7ada76fa17c67857576176d0b60f.tar.xz wireguard-linux-5e6775abb5ce7ada76fa17c67857576176d0b60f.zip | |
drm/amdgpu/dce10: Re-set VBLANK interrupt state when enabling a CRTC
This doesn't seem strictly necessary with Tonga right now, but that might
change with future power management enhancements.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions