diff options
| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-06-17 16:57:55 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-06-19 20:00:55 +0200 |
| commit | 62ab7ac5be90392a9ac0955febab778ebf51bc0a (patch) | |
| tree | 391c2f50fd3eba64a896e25853b08c187754c037 /tools/perf/scripts/python | |
| parent | dt-bindings: clock: renesas,cpg-mssr: Document RZ/T2H support (diff) | |
| download | wireguard-linux-62ab7ac5be90392a9ac0955febab778ebf51bc0a.tar.xz wireguard-linux-62ab7ac5be90392a9ac0955febab778ebf51bc0a.zip | |
dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
Add the Peripheral Module Clock L (PCLKL) core clock ID for the RZ/T2H
(R9A09G077) SoC. This clock is used by peripherals such as IIC, WDT,
and others.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250617155757.149597-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions