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| author |   Stephen Boyd <sboyd@kernel.org> | 2025-07-31 09:10:06 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-07-31 09:10:06 -0700 |
| commit | 64c21f253a3737c15ab745e9276b2352d86aed26 (patch) | |
| tree | 89e92ac84c4a2971104fcd8c7a09620559cf5cba /tools/perf/scripts/python | |
| parent | Merge branch 'clk-pm' into clk-next (diff) | |
| parent | Merge tag 'sunxi-clk-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes (diff) | |
| download | wireguard-linux-64c21f253a3737c15ab745e9276b2352d86aed26.tar.xz wireguard-linux-64c21f253a3737c15ab745e9276b2352d86aed26.zip | |
Merge branch 'clk-fixes' into clk-next
Resolve conflicts with i.MX95 changes 88768d6f8c13 ("clk:
imx95-blk-ctl: Rename lvds and displaymix csr blk") in clk-imx
and aacc875a448d ("clk: imx: Fix an out-of-bounds access in
dispmix_csr_clk_dev_data") in clk-fixes.
* clk-fixes:
clk: sunxi-ng: v3s: Fix TCON clock parents
clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name
clk: sunxi-ng: v3s: Fix CSI SCLK clock name
dt-bindings: clock: mediatek: Add #reset-cells property for MT8188
clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data
clk: scmi: Handle case where child clocks are initialized before their parents
clk: sunxi-ng: a523: Mark MBUS clock as critical
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions