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| author |   Ben Zong-You Xie <ben717@andestech.com> | 2025-07-11 21:30:21 +0800 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2025-07-21 16:51:52 +0200 |
| commit | 65bbf10b934ae17e1ce7a673355723eb806668ac (patch) | |
| tree | a7ca32027a179b9b767e52528158e072019b496a /tools/perf/scripts/python | |
| parent | dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller (diff) | |
| download | wireguard-linux-65bbf10b934ae17e1ce7a673355723eb806668ac.tar.xz wireguard-linux-65bbf10b934ae17e1ce7a673355723eb806668ac.zip | |
dt-bindings: timer: add Andes machine timer
Add the DT binding documentation for Andes machine timer.
The RISC-V architecture defines a machine timer that provides a real-time
counter and generates timer interrupts. Andes machiner timer (PLMT0) is
the implementation of the machine timer, and it contains memory-mapped
registers (mtime and mtimecmp). This device supports up to 32 cores.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-6-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions