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| author |   Diederik de Haas <didi.debian@cknow.org> | 2025-07-09 15:15:17 +0200 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2025-07-15 20:19:23 +0200 |
| commit | 776d8e75d4a3a422a680648e30c5bfe607a99805 (patch) | |
| tree | ee81fa0991d56ef20f82c5ef3f8b83b24f8f8189 /tools/perf/scripts/python | |
| parent | arm64: dts: rockchip: Move dsi address+size-cells from SoC to rk3399 boards (diff) | |
| download | wireguard-linux-776d8e75d4a3a422a680648e30c5bfe607a99805.tar.xz wireguard-linux-776d8e75d4a3a422a680648e30c5bfe607a99805.zip | |
arm64: dts: rockchip: Simplify VOP port definition on rk3328
When there's only 1 endpoint, there is no need for a unit-address and
removing that allows removing of related properties as well.
This fixes the following DTB validation warnings:
graph node has single child node 'endpoint@0',
#address-cells/#size-cells are not necessary
Signed-off-by: Diederik de Haas <didi.debian@cknow.org>
Link: https://lore.kernel.org/r/20250709132323.128757-5-didi.debian@cknow.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions