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| author |   Conor Dooley <conor.dooley@microchip.com> | 2022-08-10 09:59:15 +0100 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2022-08-15 21:07:41 +0100 |
| commit | 7eac0081a8e958106ed3aea402c8105f30fad6d9 (patch) | |
| tree | 3c3f672a16c6357efee8c61e0e50005d3ae2a0e4 /tools/perf/scripts/python | |
| parent | Merge tag 'riscv-for-linus-5.20-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux (diff) | |
| download | wireguard-linux-7eac0081a8e958106ed3aea402c8105f30fad6d9.tar.xz wireguard-linux-7eac0081a8e958106ed3aea402c8105f30fad6d9.zip | |
riscv: dts: microchip: add qspi compatible fallback
The "hard" QSPI peripheral on PolarFire SoC is derived from version 2
of the FPGA IP core. The original binding had no fallback etc, so this
device tree is valid as is. There was also no functional driver for the
QSPI IP, so no device with a devicetree from a previous mainline
release will regress.
Link: https://lore.kernel.org/linux-spi/7c9f0d96-2882-964a-cd1f-916ddb3f0410@linaro.org/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions