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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-06-24 16:30:49 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-07-02 20:38:06 +0200 |
| commit | 8250a8a9b10f459a40460104e6d6064c98283d1e (patch) | |
| tree | a7c1a8f63f4b82b8d5c0a2b1d6b349ffe725fed9 /tools/perf/scripts/python | |
| parent | clk: renesas: r9a09g057: Add entries for the RSPIs (diff) | |
| download | wireguard-linux-8250a8a9b10f459a40460104e6d6064c98283d1e.tar.xz wireguard-linux-8250a8a9b10f459a40460104e6d6064c98283d1e.zip | |
clk: renesas: rzv2h: Drop redundant base pointer from pll_clk
The base address can be accessed via the priv pointer already present in
struct pll_clk, making the separate base field redundant. Remove the base
member and its assignment.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250624153049.462535-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions