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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2025-07-31 16:12:16 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-07-31 16:12:16 -0500 |
| commit | 90eb421c46fd7e31f03b4e5f8a36eb81ca3f42bb (patch) | |
| tree | 00d551cc35283b364b1d859599d9b93b8a95e648 /tools/perf/scripts/python | |
| parent | Merge branch 'pci/controller/qcom' (diff) | |
| parent | PCI: rockchip: Set Target Link Speed to 5.0 GT/s before retraining (diff) | |
| download | wireguard-linux-90eb421c46fd7e31f03b4e5f8a36eb81ca3f42bb.tar.xz wireguard-linux-90eb421c46fd7e31f03b4e5f8a36eb81ca3f42bb.zip | |
Merge branch 'pci/controller/rockchip'
- Drop unused PCIe Message routing and code definitions (Hans Zhang)
- Use standard PCIe config register definitions instead of
rockchip-specific redefinitions (Geraldo Nascimento)
- Set Target Link Speed to 5.0 GT/s before retraining so we have a chance
to train at a higher speed (Geraldo Nascimento)
* pci/controller/rockchip:
PCI: rockchip: Set Target Link Speed to 5.0 GT/s before retraining
PCI: rockchip: Use standard PCIe definitions
PCI: rockchip: Remove redundant PCIe message routing definitions
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions