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| author |   Xiao Wang <xiao.w.wang@intel.com> | 2023-09-21 22:16:52 +0800 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2023-10-31 19:15:53 -0700 |
| commit | 92235d3d8365d24f6cc6701b545e764ef144806a (patch) | |
| tree | 4ebcf997b9a3f9f417d804fecbd4b2bd5ed6e094 /tools/perf/scripts/python | |
| parent | RISC-V: clarify the QEMU workaround in ISA parser (diff) | |
| download | wireguard-linux-92235d3d8365d24f6cc6701b545e764ef144806a.tar.xz wireguard-linux-92235d3d8365d24f6cc6701b545e764ef144806a.zip | |
riscv/mm: Fix the comment for swap pte format
Swap type takes bits 7-11 and swap offset should start from bit 12.
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Link: https://lore.kernel.org/r/20230921141652.2657054-1-xiao.w.wang@intel.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions