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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2017-11-14 12:11:20 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-11-14 12:11:20 -0600 |
| commit | 9c42da50c068bd3f54cd6248efd9c92d118918ed (patch) | |
| tree | 7e39c0b9aa2cdcc697c06d3f22a53bf9184dfb45 /tools/perf/scripts/python | |
| parent | Merge branch 'pci/aer' into next (diff) | |
| parent | PCI/ASPM: Add L1 Substates definitions (diff) | |
| download | wireguard-linux-9c42da50c068bd3f54cd6248efd9c92d118918ed.tar.xz wireguard-linux-9c42da50c068bd3f54cd6248efd9c92d118918ed.zip | |
Merge branch 'pci/aspm' into next
* pci/aspm:
PCI/ASPM: Add L1 Substates definitions
PCI/ASPM: Reformat ASPM register definitions
PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD
PCI/ASPM: Account for downstream device's Port Common_Mode_Restore_Time
PCI/ASPM: Deal with missing root ports in link state handling
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions