diff options
| author |   Stephen Boyd <sboyd@kernel.org> | 2025-07-21 17:20:15 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-07-21 17:20:15 -0700 |
| commit | a0a6f598e34312793c75bf1a63eeb9c4bd572427 (patch) | |
| tree | 1e97ced4455cc0ee0b79556da6087d2979a0a23a /tools/perf/scripts/python | |
| parent | Linux 6.16-rc1 (diff) | |
| parent | clk: rockchip: rk3568: Add PLL rate for 132MHz (diff) | |
| download | wireguard-linux-a0a6f598e34312793c75bf1a63eeb9c4bd572427.tar.xz wireguard-linux-a0a6f598e34312793c75bf1a63eeb9c4bd572427.zip | |
Merge tag 'v6.17-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull a Rockchip clk driver update from Heiko Stuebner:
- 132MHz PLL rate for Rockchip rk3588
* tag 'v6.17-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rk3568: Add PLL rate for 132MHz
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions