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| author |   Rice Lee <ot_riceyj.lee@mediatek.com> | 2025-07-22 16:57:20 +0800 |
|---|---|---|
| committer |   Martin K. Petersen <martin.petersen@oracle.com> | 2025-07-24 22:48:03 -0400 |
| commit | a28f98103890403717008a3a016744721f87b03e (patch) | |
| tree | 0527e6da15411178c66f3a90d29fbc42ef3768dd /tools/perf/scripts/python | |
| parent | scsi: dt-bindings: mediatek,ufs: add MT8195 compatible and update clock nodes (diff) | |
| download | wireguard-linux-a28f98103890403717008a3a016744721f87b03e.tar.xz wireguard-linux-a28f98103890403717008a3a016744721f87b03e.zip | |
scsi: arm64: dts: mediatek: mt8195: Add UFSHCI node
Add a UFS host controller interface (UFSHCI) node to mt8195.dtsi.
Introduce the 'mediatek,ufs-disable-mcq' property to allow disabling
Multiple Circular Queue (MCQ) support.
Signed-off-by: Rice Lee <ot_riceyj.lee@mediatek.com>
Signed-off-by: Eric Lin <ht.lin@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Link: https://lore.kernel.org/r/20250722085721.2062657-4-macpaul.lin@mediatek.com
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions