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author | 2021-03-31 22:42:16 +0200 | |
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committer | 2021-08-06 09:30:00 +0200 | |
commit | a7056e0423725e21797e72e5c41b2cb535784d3c (patch) | |
tree | f320c8dd3f7a05cb4e52d27c9cdc9898a59b8151 /tools/perf/scripts/python | |
parent | Linux 5.14-rc1 (diff) | |
download | wireguard-linux-a7056e0423725e21797e72e5c41b2cb535784d3c.tar.xz wireguard-linux-a7056e0423725e21797e72e5c41b2cb535784d3c.zip |
ARM: dts: sti: update flexgen compatible within stih418-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions