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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2024-08-05 14:17:05 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-08-23 15:50:04 +0200 |
| commit | a94a244a5b1a2040611aaaa17fd23dd908bc01ac (patch) | |
| tree | 2b1dc91f30cbb57b3b3214dc178efdbc087767fa /tools/perf/scripts/python | |
| parent | arm64: dts: renesas: r9a07g044: Correct GICD and GICR sizes (diff) | |
| download | wireguard-linux-a94a244a5b1a2040611aaaa17fd23dd908bc01ac.tar.xz wireguard-linux-a94a244a5b1a2040611aaaa17fd23dd908bc01ac.zip | |
arm64: dts: renesas: r9a07g043u: Add FCPVD node
Add FCPVD node to RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240805131709.101679-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions