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| author |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-07-01 14:07:39 +0200 |
|---|---|---|
| committer |   Dave Jiang <dave.jiang@intel.com> | 2025-07-01 08:12:57 -0700 |
| commit | ac0fe6a5731700bcea6fecfd5d0b76c0454b3a20 (patch) | |
| tree | 2e0cbd1d2a7d19ff3c3f913216d0105f4f6b4ace /tools/perf/scripts/python | |
| parent | cxl/edac: Use correct format specifier for u32 val (diff) | |
| download | wireguard-linux-ac0fe6a5731700bcea6fecfd5d0b76c0454b3a20.tar.xz wireguard-linux-ac0fe6a5731700bcea6fecfd5d0b76c0454b3a20.zip | |
cxl: make cxl_bus_type constant
Now that the driver core can properly handle constant struct bus_type,
move the cxl_bus_type variable to be a constant structure as well,
placing it into read-only memory which can not be modified at runtime.
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: Dave Jiang <dave.jiang@intel.com>
Cc: Alison Schofield <alison.schofield@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: linux-cxl@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://patch.msgid.link/2025070138-vigorous-negative-eae7@gregkh
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions