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| author |   Ben Zong-You Xie <ben717@andestech.com> | 2025-07-11 21:30:24 +0800 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2025-07-21 16:51:52 +0200 |
| commit | ad087c91eb87bebd79f05a4c9b5cfbe72d6186fa (patch) | |
| tree | 167c282097661ae4d4ee1612441a343651203b1e /tools/perf/scripts/python | |
| parent | riscv: dts: andes: add Voyager board device tree (diff) | |
| download | wireguard-linux-ad087c91eb87bebd79f05a4c9b5cfbe72d6186fa.tar.xz wireguard-linux-ad087c91eb87bebd79f05a4c9b5cfbe72d6186fa.zip | |
riscv: defconfig: enable Andes SoC
Enable Andes SoC config in defconfig to allow the default
upstream kernel to boot on Voyager board.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-9-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions