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| author |   Zhang Rui <rui.zhang@intel.com> | 2025-06-25 10:05:22 +0800 |
|---|---|---|
| committer |   Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2025-06-30 20:34:57 +0200 |
| commit | afc6a5b12b62c7743fb96fe27864604d7b33a5d2 (patch) | |
| tree | 652df5c9080e82ce6cf2f277decd45cfc96a164b /tools/perf/scripts/python | |
| parent | powercap: intel_rapl: Do not change CLAMPING bit if ENABLE bit cannot be changed (diff) | |
| download | wireguard-linux-afc6a5b12b62c7743fb96fe27864604d7b33a5d2.tar.xz wireguard-linux-afc6a5b12b62c7743fb96fe27864604d7b33a5d2.zip | |
powercap: intel_rapl_msr: Add PL4 support for Panther Lake
Add Panther Lake to the list of processors where PL4 is supported.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Link: https://patch.msgid.link/20250625020522.253548-1-rui.zhang@intel.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions