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| author |   Chris Packham <chris.packham@alliedtelesis.co.nz> | 2023-07-03 15:50:42 +1200 |
|---|---|---|
| committer |   Miquel Raynal <miquel.raynal@bootlin.com> | 2023-07-15 18:05:38 +0200 |
| commit | bd60fcf27654d2acbb1f0d115daefaac6118b74c (patch) | |
| tree | 4befd7d3133cd7c9c3640c5d6b77f7758347a88f /tools/perf/scripts/python | |
| parent | mtd: rawnand: qcom: Remove legacy interface (diff) | |
| download | wireguard-linux-bd60fcf27654d2acbb1f0d115daefaac6118b74c.tar.xz wireguard-linux-bd60fcf27654d2acbb1f0d115daefaac6118b74c.zip | |
dt-bindings: mtd: Add AC5 specific binding
Add binding for AC5 SoC. This SoC only supports NAND SDR timings up to
mode 3 so a specific compatible value is needed.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20230703035044.2063303-2-chris.packham@alliedtelesis.co.nz
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions