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| author |   Imre Deak <imre.deak@intel.com> | 2025-08-11 11:01:51 +0300 |
|---|---|---|
| committer |   Tvrtko Ursulin <tursulin@ursulin.net> | 2025-08-18 08:08:20 +0100 |
| commit | c5c2b4b3841666be3a45346d0ffa96b4b143504e (patch) | |
| tree | 4cc8cdac9e31a4b0058877477fe209b3171bc0a0 /tools/perf/scripts/python | |
| parent | drm/i915/lnl+/tc: Fix max lane count HW readout (diff) | |
| download | wireguard-linux-c5c2b4b3841666be3a45346d0ffa96b4b143504e.tar.xz wireguard-linux-c5c2b4b3841666be3a45346d0ffa96b4b143504e.zip | |
drm/i915/lnl+/tc: Use the cached max lane count value
Use the cached max lane count value on LNL+, to account for scenarios
where this value is queried after the HW cleared the corresponding pin
assignment value in the TCSS_DDI_STATUS register after the sink got
disconnected.
For consistency, follow-up changes will use the cached max lane count
value on other platforms as well and will also cache the pin assignment
value in a similar way.
Cc: stable@vger.kernel.org # v6.8+
Reported-by: Charlton Lin <charlton.lin@intel.com>
Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/20250811080152.906216-5-imre.deak@intel.com
(cherry picked from commit afc4e84388079f4d5ba05271632b7a4d8d85165c)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions