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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-22 13:50:33 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-30 10:44:18 +0200 |
| commit | ccdf745bd10f0682bfd87ba5612fabdf57ff1d5b (patch) | |
| tree | 7ff5161de63c2f254a26f9ab8352cb0763e5e653 /tools/perf/scripts/python | |
| parent | clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs (diff) | |
| download | wireguard-linux-ccdf745bd10f0682bfd87ba5612fabdf57ff1d5b.tar.xz wireguard-linux-ccdf745bd10f0682bfd87ba5612fabdf57ff1d5b.zip | |
clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type
The variable PLL2 clock type was superseded by the more generic
variable fractional 8.25 PLL clock type, and its sole user was converted.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/8e5564958002351f29435f63de1304fb3b51a725.1721648548.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions