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| author |   Chen-Yu Tsai <wens@csie.org> | 2015-11-29 11:03:10 +0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@free-electrons.com> | 2015-12-01 14:07:51 +0100 |
| commit | d255abd60e9c0c91e0146fdcbe534b3b9f5352a6 (patch) | |
| tree | 17f9eae1fc6479ba71f44678294810fce78e1e68 /tools/perf/scripts/python | |
| parent | ARM: dts: sun9i: Add A80 PRCM clocks and reset control nodes (diff) | |
| download | wireguard-linux-d255abd60e9c0c91e0146fdcbe534b3b9f5352a6.tar.xz wireguard-linux-d255abd60e9c0c91e0146fdcbe534b3b9f5352a6.zip | |
ARM: dts: sun9i: Add TODO comments for the main and low power clocks
The main (24MHz) clock on the A80 is configurable via the PRCM address
space. The low power/speed (32kHz) clock is from an external chip, the
AC100.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions