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author | 2024-10-28 13:51:50 +0800 | |
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committer | 2024-11-08 11:45:29 -0500 | |
commit | d4be16ccfd5bf822176740a51ff2306679a2247e (patch) | |
tree | 6a52e0c7e616ad906e94f5fd2e9dae7c15116ff7 /tools/perf/scripts/python | |
parent | drm/amdgpu: Inform if PCIe based P2P links are not available (diff) | |
download | wireguard-linux-d4be16ccfd5bf822176740a51ff2306679a2247e.tar.xz wireguard-linux-d4be16ccfd5bf822176740a51ff2306679a2247e.zip |
drm/amd/pm: print pp_dpm_mclk in ascending order on SMU v14.0.0
Currently, the pp_dpm_mclk values are reported in descending order
on SMU IP v14.0.0/1/4. Adjust to ascending order for consistency
with other clock interfaces.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions