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| author |   Peter Chen <peter.chen@freescale.com> | 2014-02-24 10:20:56 +0800 |
|---|---|---|
| committer |   Felipe Balbi <balbi@ti.com> | 2014-03-05 14:40:07 -0600 |
| commit | d9c130328d2e4b09c0c689e5d3144c0d955ce966 (patch) | |
| tree | 7e76d90c4efc6e5dc54cb3800435778efe735d46 /tools/perf/scripts/python | |
| parent | usb: phy: mxs: Add auto clock and power setting (diff) | |
| download | wireguard-linux-d9c130328d2e4b09c0c689e5d3144c0d955ce966.tar.xz wireguard-linux-d9c130328d2e4b09c0c689e5d3144c0d955ce966.zip | |
usb: doc: phy-mxs: update binding for adding anatop phandle
Add anatop phandle which is used to access anatop registers to
control PHY's power and other USB operations.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions