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| author |   Ard Biesheuvel <ardb@kernel.org> | 2024-02-14 13:29:15 +0100 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2024-02-16 12:42:38 +0000 |
| commit | db95ea787bd19be666ba41733259ffea65963bff (patch) | |
| tree | 4b5b859adaad022e80f6140f4bd62d02b470c0e1 /tools/perf/scripts/python | |
| parent | arm64: Add ESR decoding for exceptions involving translation level -1 (diff) | |
| download | wireguard-linux-db95ea787bd19be666ba41733259ffea65963bff.tar.xz wireguard-linux-db95ea787bd19be666ba41733259ffea65963bff.zip | |
arm64: mm: Wire up TCR.DS bit to PTE shareability fields
When LPA2 is enabled, bits 8 and 9 of page and block descriptors become
part of the output address instead of carrying shareability attributes
for the region in question.
So avoid setting these bits if TCR.DS == 1, which means LPA2 is enabled.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20240214122845.2033971-74-ardb+git@google.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions