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| author |   Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> | 2025-07-03 02:56:28 -0700 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2025-07-22 17:53:11 +0530 |
| commit | dfef90f29811b5b8bc6353e259cac6134a88671f (patch) | |
| tree | 600fb563c9c792180cd3b2881c28ee8d8f8af4bf /tools/perf/scripts/python | |
| parent | phy: qcom: qmp-combo: Add missing PLL (VCO) configuration on SM8750 (diff) | |
| download | wireguard-linux-dfef90f29811b5b8bc6353e259cac6134a88671f.tar.xz wireguard-linux-dfef90f29811b5b8bc6353e259cac6134a88671f.zip | |
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for QCS615
QCS615 pcie phy only use 5 clocks, which are aux, cfg_ahb, ref,
ref_gen, pipe. So move "qcom,qcs615-qmp-gen3x1-pcie-phy" compatible
from 6 clocks' list to 5 clocks' list.
Fixes: 1e889f2bd837 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS615 QMP PCIe PHY Gen3 x1")
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20250703095630.669044-2-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions