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| author |   Matt Coster <matt.coster@imgtec.com> | 2025-04-10 10:55:14 +0100 |
|---|---|---|
| committer | Matt Coster <matt.coster@imgtec.com> | 2025-04-15 12:21:52 +0100 |
| commit | f0a1ab65d90420f2817569bbf67111feb8e6821e (patch) | |
| tree | af33c3353243dbb77a6af4430140d8ded64ba5e3 /tools/perf/scripts/python | |
| parent | drm/imagination: Add RISC-V firmware processor support (diff) | |
| download | wireguard-linux-f0a1ab65d90420f2817569bbf67111feb8e6821e.tar.xz wireguard-linux-f0a1ab65d90420f2817569bbf67111feb8e6821e.zip | |
drm/imagination: Use cached memory with dma_coherent
The TI k3-j721s2 platform does not allow us to use uncached memory
(which is what the driver currently does) without disabling cache snooping
on the AXI ACE-Lite interface, which would be too much of a performance
hit.
Given the platform is dma-coherent, we can simply force all
device-accessible memory allocations through the CPU cache. In fact, this
can be done whenever the dma_coherent attribute is present.
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-15-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions