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| author |   Rafał Miłecki <rafal@milecki.pl> | 2024-04-05 12:50:30 +0200 |
|---|---|---|
| committer |   AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2024-06-27 10:10:22 +0200 |
| commit | f80cfe9616b7448eca709a3e87ca57201cd5787c (patch) | |
| tree | 40285274b93797f5da0641b4889e5d35dbf3ff61 /tools/perf/scripts/python | |
| parent | arm64: dts: mediatek: mt7986a: bpi-r3: Convert to sugar syntax (diff) | |
| download | wireguard-linux-f80cfe9616b7448eca709a3e87ca57201cd5787c.tar.xz wireguard-linux-f80cfe9616b7448eca709a3e87ca57201cd5787c.zip | |
arm64: dts: mediatek: mt7981: fix code alignment for PWM clocks
Align "clocks" array entries to start at the same column.
Fixes: cf29427573cc ("arm64: dts: mediatek: Add initial MT7981B and Xiaomi AX3000T")
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20240405105030.24559-1-zajec5@gmail.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions